1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device including power semiconductor elements as power switching elements, and to a method of manufacturing the same.
2. Description of the Related Art
Recently, there is a great demand for small-sized and high-performance power apparatuses in the power electronics field. In order to meet the demand, power semiconductor elements require improvement of performance with respect to high breakdown voltage, large current, low power loss, high speed and high ruggedness. In the power semiconductor elements, a power MOSFET has high-speed switching performance; therefore, the power MOSFET is frequently used as the key device in the switch mode power supply field.
FIG. 62 is a cross-sectional view showing a conventional power MOSFET. In FIG. 62, a reference numeral 101 denotes a low-resistance n-type drain layer, and a high-resistance n-type base layer 102 is provided on the n-type drain layer 101. The surface of the n-type base layer 102 is selectively formed with a p-type base layer 103, and the surface of the p-type base layer 103 is selectively formed with an n-type source layer 104. A gate electrode 106 is provided on the p-type base layer 103 between n-type source and base layers 104 and 102 via a gate insulating film 105.
A drain electrode 107 is provided on the n-type drain layer 101, and a source electrode 108 is provided on the n-type source layer 104 and the p-type base layer 103.
When this kind of power MOSFET is in on state, the surface of the n-type base layer 103 under the gate electrode 106 is formed with an n-channel; therefore, electronic current flows between the source and drain. The conventional power MOSFET is a majority carrier device; therefore, it has advantages that there is no storage time of minority carriers, and switching speed is high.
However, because of no conductivity modulation, the power MOSFET is disadvantageous to on-resistance as compared with power semiconductor elements such as insulated gate bipolar transistor (IGBT). For this reason, on-resistance is easy to become high. The point relating to on-resistance will be explained in the following.
FIG. 63 shows an electric field distribution in off-state in cross section taken along an arrow line 63A–63A′ of FIG. 62. In the conventional power MOSFET shown in FIG. 62, the following relationship is established between the electric field E of the n-type base layer 102, distance (width) y and impurity concentration N. That is, the relationship is dE/dy=N/ε (ε is permittivity of semiconductor material of power MOSFET). The breakdown voltage (Vb) of the element is determined by the equation Vb=∫E·dy. Namely, the larger the area of the electric field distribution of the n-type base layer 102 is, the higher the breakdown voltage of element becomes.
In fact, the breakdown voltage of element receives the influence on the area of the electric field distributions of the n-type drain layer 101 and p-type base layer 103. However, the area of these electric field distributions is disregarded because it is very small as compared with the area of the electric field distribution of the n-type base layer 102.
In order to make large the area of electric field distribution of the element, the following means are taken. One is to make thick the n-type base layer 102, and another is to reduce the impurity concentration of the n-type base layer 102. But, these means increase the resistance of the n-type base layer 102; as a result, on-resistance is stepped up. Therefore, the more high breakdown voltage is improved, the higher on-resistance becomes.
There has been known a power MOSFET having the structure shown in FIG. 64 as the power MOSFET solving the problem described above. The power MOSFET has a drift layer in which pillar-shaped n-type and p-type drift layers 109 and 110 are alternately and repeatedly arrayed in place of the high resistance n-type base layer 103.
In this kind of power MOSFET, the impurity concentration of the n-type drift layer 109 is set higher in order to reduce on-resistance. In this case, the element is designed in the following manner, and thereby, the same breakdown voltage as the power MOSFET of FIG. 62 is obtained. That is, in the off-state, before breakdown occurs, n-type and p-type drift layers 109 and 110 are fully depleted by the depletion layer laterally extending from the junction between n-type and p-type drift layers 109 and 110.
In the power MOSFET of FIG. 64, if the total amount of n-type impurities of the n-type drift layer 109 is the same as that of p-type impurities of the p-type drift layer 110, the breakdown voltage is constant. In this case, the breakdown voltage is constant regardless of the n-type impurity concentration of the n-type drift layer 109. Therefore, the n-type impurity concentration is increased without varying the total amount of n-type impurities of the n-type drift layer 109, thereby reducing on-resistance.
In order to increase the n-type impurity concentration of the n-type drift layer 109, the width of the n-type drift layer 109 must be made narrow.
For example, the p-type drift layer 110 is formed by ion implantation of p-type impurities to an n-type substrate and heat treatment. On the other hand, the n-type drift layer 109 is formed as the remains of the n-type region where p-type impurities are not diffused. For this reason, if the width of the n-type drift layer 109 becomes narrow, the following influences are greatly given. One is the influence of diffusion. accuracy of the p-type impurities in heat treatment. Another is the influence of counter dope (i.e., n-type and p-type impurity concentrations compete, and the n-type drift layer is made low concentration or becomes a neutral region). As a result, it is difficult to obtain the n-type drift layer having the desired narrow width and high n-type impurity concentration.
Namely, the element structure of FIG. 64 is effective to reduction of on-resistance; however, it is difficult to increase the net n-type impurity concentration of the n-type drift layer 109. For this reason, in the current stage, it is difficult to sufficiently reduce on-resistance.
FIG. 65 shows the structure of a junction termination region JTR of the power MOSFET of FIG. 64. In FIG. 65, a dicing line DL is also shown. In the junction termination region JTR, the n-type drift layer 109 and the p-type drift layer 110 are alternately repeatedly formed. However, no p-type drift layer 110 is formed in the region from the end of a cell region CR with a predetermined distance to the chip end. Only n-type drift layer 109 (n-type base layer) is formed in the region described above.
The surface of the n-type drift layer 109 of the chip end is formed with a high concentration n-channel stopper layer 111, and an electrode 112 is formed on the n-channel stopper layer 111.
The method of manufacturing the power MOSFET having the junction termination region will be described with reference to FIG. 66.
A substrate including the n-type drain layer 101 is prepared (step S11). The n-type and the p-type drift layers 109 and 110 are formed on the substrate by repeating epitaxial growth of an n-type silicon layer (step S12) and ion implantation of p-type impurities (step S13).
More specifically, the n-type silicon layer constituting part of the n-type drift layer 109 epitaxially grows on the substrate by a predetermined thickness (step S12).
Resist having an opening on a forming region of the p-type drift layer 110 is formed on the n-type silicon layer using the publicly known photolithography process. Thereafter, p-type impurity (e.g., boron) is implanted into the n-type silicon layer, using the resist as a mask. Anneal (activation anneal) for activating the p-type impurity is carried out. As a result, a p-type silicon layer constituting part of the p-type drift layer 110 is formed by a predetermined thickness (step S13).
The steps S12 and S13 are repeated until the n-type and p-type silicon layers becomes a predetermined thickness, that is, the n-type and p-type drift layers 109 and 110 having a predetermined thickness are obtained. In the manner described above, a wafer in which the n-type and p-type drift layers 109 and 110 are formed on the n-type drain layer 101 is obtained (step S14).
Thereafter, the MOSFET structure is formed on the wafer surface by the publicly know process (step S15). Finally, a chip including a power MOSFET is cut from the wafer.
In the power semiconductor element, if current rating is different even when the breakdown voltage is the same, it is general that the number (area) of the n-type and p-type drift layers 109 and 110 is different. Therefore, if current rating is different even when the breakdown voltage of the power semiconductor element built in the wafer is the same, the chip size is different in general.
As described above, ion implantation of the p-type impurity is employed to form the p-type drift layer 110; As a result, different mask for ion implantation is required for each current rating (chip size).
For this reason, in step S13, different mask for ion implantation must be formed for each current rating, and in addition, different exposure mask must be formed for each different mask for ion implantation. As described above, even if the breakdown voltage is the same, different mask must be formed for each current rating. This is a factor of increasing the manufacture cost.
Likewise, different wafer (wafer formed in step S14) is required for each current rating (chip size). Thus, even when forming the element having the same breakdown voltage, different wafer is used for each current rating in step S15. This is another factor of increasing the manufacture cost.